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M27C512
512 Kbit (64Kb x8) UV EPROM and OTP EPROM
5V 10% SUPPLY VOLTAGE in READ OPERATION FAST ACCESS TIME: 45ns LOW POWER "CMOS" CONSUMPTION: - Active Current 30mA - Standby Current 100A PROGRAMMING VOLTAGE: 12.75V 0.25V PROGRAMMING TIMES of AROUND 6sec. (PRESTO IIB ALGORITHM) ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code: 3Dh
28
28
1
1
FDIP28W (F)
PDIP28 (B)
DESCRIPTION The M27C512 is a 512 Kbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for applications where fast turn-around and pattern experimentation are important requirements and is organized as 65,536 by 8 bits. The FDIP28W (window ceramic frit-seal package) has transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27C512 is offered in PDIP28, PLCC32 and TSOP28 (8 x 13.4 mm) packages.
PLCC32 (C)
TSOP28 (N) 8 x 13.4mm
Figure 1. Logic Diagram
VCC
16 A0-A15
8 Q0-Q7
E
Table 1. Signal Names
A0-A15 Q0-Q7 E GVPP VCC VSS November 1998 Address Inputs Data Outputs Chip Enable Output Enable / Program Supply Supply Voltage Ground
M27C512
GVPP
VSS
AI00761B
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M27C512
Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections
AI00762
VSS DU Q3 Q4 Q5
AI00763
A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS
28 1 27 2 26 3 25 4 24 5 23 6 22 7 M27C512 21 8 20 9 19 10 18 11 17 12 13 16 14 15
VCC A14 A13 A8 A9 A11 GVPP A10 E Q7 Q6 Q5 Q4 Q3
A7 A12 A15 DU VCC A14 A13
1 32 A6 A5 A4 A3 A2 A1 A0 NC Q0 A8 A9 A11 NC GVPP A10 E Q7 Q6 9 M27C512 25 17
Warning: NC = Not Connected, DU = Don't Use
Figure 2C. TSOP Pin Connections
GVPP A11 A9 A8 A13 A14 VCC A15 A12 A7 A6 A5 A4 A3
22
21
28 1
M27C512
15 14
7
8
AI00764B
A10 E Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2
DEVICE OPERATION The modes of operations of the M27C512 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for GVPP and 12V on A9 for Electronic Signature. Read Mode The M27C512 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M27C512 has a standby mode which reduces the active current from 30mA to 100A The M27C512 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the GVPP input.
2/15
Q1 Q2
M27C512
Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO
(2)
Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltages (except A9) Supply Voltage A9 Voltage Program Supply Voltage
(3)
Value -40 to 125 -50 to 125 -65 to 150 -2 to 7 -2 to 7 -2 to 13.5 -2 to 14
Unit C C C V V V V
VCC VA9
(2)
VPP
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is -0.5V with possible undershoot to -2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range.
Table 3. Operating Modes
Mode Read Output Disable Program Program Inhibit Standby Electronic Signature
Note: X = VIH or VIL, VID = 12V 0.5V
E VIL VIL VIL Pulse VIH VIH VIL
GVPP VIL VIH VPP VPP X VIL
A9 X X X X X VID
Q0 - Q7 Data Out Hi-Z Data In Hi-Z Hi-Z Codes
Table 4. Electronic Signature
Identifier Manufacturer's Code Device Code A0 VIL VIH Q7 0 0 Q6 0 0 Q5 1 1 Q4 0 1 Q3 0 1 Q2 0 1 Q1 0 0 Q0 0 1 Hex Data 20h 3Dh
Two Line Output Control Because EPROMs are usually used in larger memory arrays, the product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur.
For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.
3/15
M27C512
Table 5. AC Measurement Conditions
High Speed Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 10ns 0 to 3V 1.5V Standard 20ns 0.4V to 2.4V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed 3V 1.5V 0V
DEVICE UNDER TEST 3.3k 1N914
Standard 2.4V 2.0V 0.8V
AI01822
OUT CL
0.4V
CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance
AI01823B
Table 6. Capacitance (1) (TA = 25 C, f = 1 MHz )
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note. 1. Sampled only, not 100% tested.
System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output.
The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1F ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7F bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supplyconnection point.The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.
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M27C512
Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70 C, -40 to 85 C or -40 to 125 C; VCC = 5V 5% or 5V 10%; VPP = VCC)
Symbol ILI ILO ICC ICC1 ICC2 IPP VIL VIH
(2)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL Output High Voltage CMOS
Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, G = VIL, IOUT = 0mA, f = 5MHz E = VIH E > VCC - 0.2V VPP = VCC
Min
Max 10 10 30 1 100 10
Unit A A mA mA A A V V V V V
-0.3 2 IOL = 2.1mA IOH = -1mA IOH = -100A 3.6 VCC -0.7V
0.8 VCC + 1 0.4
VOL VOH
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V.
Table 8A. Read Mode AC Characteristics (1) (TA = 0 to 70 C, -40 to 85 C or -40 to 125 C; VCC = 5V 5% or 5V 10%; VPP = VCC)
M27C512 Symbol Alt Parameter Test Condition -45 (3) Min tAVQV tELQV tACC tCE Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z E = VIL, G = VIL G = VIL Max 45 45 Min -60 Max 60 60 Min -70 Max 70 70 Min -80 Max 80 80 ns ns Unit
tGLQV
tOE
E = VIL
25
30
35
40
ns
tEHQZ (2)
tDF
G = VIL
0
25
0
25
0
30
0
30
ns
tGHQZ (2)
tDF
E = VIL
0
25
0
25
0
30
0
30
ns
tAXQX
tOH
Address E = VIL, G = VIL Transition to Output Transition
0
0
0
0
ns
Notes. 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. 3. In case of 45ns speed see High Speed AC measurement conditions.
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M27C512
Table 8B. Read Mode AC Characteristics (1) (TA = 0 to 70 C, -40 to 85 C or -40 to 125 C; VCC = 5V 5% or 5V 10%; VPP = VCC)
M27C512 Symbol Alt Parameter Test Condition -90 Min tAVQV tELQV tGLQV tEHQZ (2) tGHQZ (2) tACC tCE tOE tDF tDF Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL 0 0 Max 90 90 40 30 30 0 0 -10 Min Max 100 100 40 30 30 0 0 -12 Min Max 120 120 50 40 40 0 0 -15/-20/-25 Min Max 150 150 60 50 50 ns ns ns ns ns Unit
tAXQX
tOH
E = VIL, G = VIL
0
0
0
0
ns
Notes. 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
A0-A15
VALID tAVQV tAXQX
VALID
E tGLQV G tELQV Q0-Q7 tGHQZ Hi-Z tEHQZ
AI00735B
Programming When delivered (and after each erasure for UV EPROM), all bits of the M27C512 are in the '1' state. Data is introduced by selectively programming '0's into the desired bit locations. Although only '0's will be programmed, both '1's and '0's can be present in the data word. The only way to change a '0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The M27C512 is in the programming mode when VPP input is at 12.75V and
E is pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V 0.25V. The M27C512 can use PRESTO IIB Programming Algorithm that drastically reduces the programming time (typically less than 6 seconds). Nevertheless to achieve compatibility with all programming equipments, PRESTO Programming Algorithm can be used as well.
6/15
M27C512
Table 9. Programming Mode DC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V)
Symbol ILI ICC IPP VIL VIH VOL VOH VID Parameter Input Leakage Current Supply Current Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL A9 Voltage IOL = 2.1mA IOH = -1mA 3.6 11.5 12.5 E = VIL -0.3 2 Test Condition VIL VIN VIH Min Max 10 50 50 0.8 VCC + 0.5 0.4 Unit A mA mA V V V V V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Table 10. MARGIN MODE AC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V)
Symbol tA9HVPH tVPHEL tA10HEH tA10LEH tEXA10X tEXVPX tVPXA9X Alt tAS9 tVPS tAS10 tAS10 tAH10 tVPH tAH9 Parameter VA9 High to VPP High VPP High to Chip Enable Low VA10 High to Chip Enable High (Set) VA10 Low to Chip Enable High (Reset) Chip Enable Transition to VA10 Transition Chip Enable Transition to VPP Transition VPP Transition to VA9 Transition Test Condition Min 2 2 1 1 1 2 2 Max Unit s s s s s s s
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Table 11. Programming Mode AC Characteristics (1) (TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V)
Symbol tAVEL tQVEL tVCHEL tVPHEL tVPLVPH tELEH tEHQX tEHVPX tVPLEL tELQV tEHQZ
(2)
Alt tAS tDS tVCS tOES tPRT tPW tDH tOEH tVR tDV tDFP tAH
Parameter Address Valid to Chip Enable Low Input Valid to Chip Enable Low VCC High to Chip Enable Low VPP High to Chip Enable Low VPP Rise Time Chip Enable Program Pulse Width (Initial) Chip Enable High to Input Transition Chip Enable High to VPP Transition VPP Low to Chip Enable Low Chip Enable Low to Output Valid Chip Enable High to Output Hi-Z Chip Enable High to Address Transition
Test Condition
Min 2 2 2 2 50 95 2 2 2
Max
Unit s s s s ns s s s s s ns ns
105
1 0 0 130
tEHAX
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested.
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M27C512
Figure 6. MARGIN MODE AC Waveforms
VCC
A8
A9 tA9HVPH GVPP tVPHEL E tA10HEH A10 Set tEXA10X tEXVPX tVPXA9X
A10 Reset tA10LEH
AI00736B
Note: A8 High level = 5V; A9 High level = 12V.
Figure 7. Programming and Verify Modes AC Waveforms
A0-A15 tAVEL Q0-Q7 tQVEL VCC tVCHEL GVPP tVPHEL E tELEH PROGRAM DATA IN
VALID tEHAX DATA OUT tEHQX tELQV tEHVPX tEHQZ
tVPLEL
VERIFY
AI00737
8/15
M27C512
Figure 8. Programming Flowchart
VCC = 6.25V, VPP = 12.75V SET MARGIN MODE
n=0
E = 100s Pulse NO ++n = 25 YES NO VERIFY YES Last Addr NO ++ Addr
FAIL
YES RESET MARGIN MODE CHECK ALL BYTES 1st: VCC = 6V 2nd: VCC = 4.2V
AI00738B
programmed. The verify is accomplished with G at VIL. Data should be verified with tELQV after the falling edge of E. On-Board Programming The M27C512 can be directly programmed in the application circuit. See the relevant Application Note AN620. Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25C 5C ambient temperature range that is required when programming the M27C512. To activate the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M27C512. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during Electronic Signature mode. Byte 0 (A0=VIL) represents the manufacturer code and byte 1 (A0=VIH) the device identifier code. For the STMicroelectronics M27C512, these two identifier bytes are given in Table 4 and can be read-out on outputs Q0 to Q7. ERASURE OPERATION (appl ies for UV EPROM) The erasure characteristics of the M27C512 is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 A. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 A range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M27C512 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M27C512 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27C512 window to prevent unintentional erasure. The recommended erasure procedure for the M27C512 is exposure to short wave ultraviolet light which has wavelength 2537 A. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000 W/cm2 power rating. The M27C512 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure.
9/15
PRESTO IIB Programming Algorithm PRESTO IIB Programming Algorithm allows the whole array to be programmed with a guaranteed margin, in a typical time of 6.5 seconds. This can be achieved with STMicroelectronics M27C512 due to several design innovations described in the M27C512 datasheet to improve programming efficiency and to provide adequate margin for reliability. Before starting the programming the internal MARGIN MODE circuit is set in order to guarantee that each cell is programmed with enough margin. Then a sequence of 100s program pulses are applied to each byte until a correct verify occurs. No overprogram pulses are applied since the verify in MARGIN MODE provides the necessary margin. Program Inhibit Programming of multiple M27C512s in parallel with different data is also easily accomplished. Except for E, all like inputs including GVPP of the parallel M27C512 may be common. A TTL low level pulse applied to a M27C512's E input, with VPP at 12.75V, will program that M27C512. A high level E input inhibits the other M27C512s from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly
M27C512
ORDERING INFORMATION SCHEME Example: M27C512 -70 X C 1 TR
Speed -45
(1)
VCC Tolerance X blank 5% 10% F B C N
Package FDIP28W PDIP28 PLCC32 TSOP28 8 x 13.4mm
Temperature Range 1 6 3 0 to 70 C -40 to 85 C -40 to 125 C TR X
Option Additional Burn-in Tape & Reel Packing
45 ns 60 ns 70 ns 80 ns 90 ns 100 ns 120 ns 150 ns 200 ns 250 ns
-60 -70 -80 -90 -10 -12 -15 -20 -25
Note: 1. High Speed, see AC Characteristics section for further information
For a list of available options (Speed, V CC Tolerance, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
10/15
M27C512
FDIP28W - 28 pin Ceramic Frit-seal DIP, with window
Symb Typ A A1 A2 A3 B B1 C D D2 E E1 e eA eB L S N 7.11 2.54 14.99 33.02 15.24 1.45 0.51 3.91 3.89 0.41 - 0.23 36.50 - - 13.06 - - 16.18 3.18 1.52 - 4 28 2.49 - 11 0.280 mm Min Max 5.72 1.40 4.57 4.50 0.56 - 0.30 37.34 - - 13.36 - - 18.03 0.100 0.590 1.300 0.600 0.057 0.020 0.154 0.153 0.016 - 0.009 1.437 - - 0.514 - - 0.637 0.125 0.060 - 4 28 0.098 - 11 Typ inches Min Max 0.225 0.055 0.180 0.177 0.022 - 0.012 1.470 - - 0.526 - - 0.710
A2
A3 A1 B1 B D2 D S
N 1
A L eA eB C
e
E1
E
FDIPW-a
Drawing is not to scale
11/15
M27C512
PDIP28 - 28 pin Plastic DIP, 600 mils width
Symb Typ A A1 A2 B B1 C D D2 E E1 e1 eA eB L S N 2.54 14.99 33.02 15.24 1.52 mm Min - 0.38 3.56 0.38 - 0.20 36.83 - - 13.59 - - 15.24 3.18 1.78 0 28 Max 5.08 - 4.06 0.51 - 0.30 37.34 - - 13.84 - - 17.78 3.43 2.08 10 0.100 0.590 1.300 0.600 0.060 Typ inches Min - 0.015 0.140 0.015 - 0.008 1.450 - - 0.535 - - 0.600 0.125 0.070 0 28 Max 0.200 - 0.160 0.020 - 0.012 1.470 - - 0.545 - - 0.700 0.135 0.082 10
A2 A1 B1 B D2 D S
N
A L eA eB C
e1
E1
1
E
PDIP
Drawing is not to scale
12/15
M27C512
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
Symb Typ A A1 A2 B B1 D D1 D2 E E1 E2 e F R N Nd Ne CP 0.89 1.27 mm Min 2.54 1.52 - 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 - 0.00 - 32 7 9 0.10 Max 3.56 2.41 0.38 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 - 0.25 - 0.035 0.050 Typ inches Min 0.100 0.060 - 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 - 0.000 - 32 7 9 0.004 Max 0.140 0.095 0.015 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530 - 0.010 -
D D1
1N
A1 A2
B1
Ne
E1 E
F 0.51 (.020)
D2/E2 B
e
1.14 (.045)
Nd
A R CP
PLCC
Drawing is not to scale
13/15
M27C512
TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm
Symb Typ A A1 A2 B C D D1 E e L N CP 0.55 0.95 0.17 0.10 13.20 11.70 7.90 - 0.50 0 28 0.10 mm Min Max 1.25 0.20 1.15 0.27 0.21 13.60 11.90 8.10 - 0.70 5 0.022 0.037 0.007 0.004 0.520 0.461 0.311 - 0.020 0 28 0.004 Typ inches Min Max 0.049 0.008 0.045 0.011 0.008 0.535 0.469 0.319 - 0.028 5
A2
22 21
e
28 1
E B
7 8
D1 D
A CP
DIE
C
TSOP-c
Drawing is not to scale
A1
L
14/15
M27C512
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1998 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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